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ISL22429
Dual Digitally Controlled Potentiometer (XDCPTM)
Data Sheet September 26, 2006 FN6332.1
Low Noise, Low Power, SPI(R) Bus, 128 Taps, Wiper Only
The ISL22429 integrates two digitally controlled potentiometers (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI serial interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the contents of the DCP's IVR to the corresponding WR. The DCP can be used as a voltage divider in a wide variety of applications including control, parameter adjustments, AC measurement and signal processing.
Features
* Two potentiometers in one package * 128 resistor taps * SPI serial interface * Non-volatile storage of wiper position * Wiper resistance: 70 typical @ 3.3V * Shutdown mode * Shutdown current 5A max * Power supply: 2.7V to 5.5V * 50k or 10k total resistance * High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T < +55C * 10 Lead MSOP
Pinout
ISL22429 (10 LD MSOP) TOP VIEW
NC SCK SDO GND RW1 1 2 3 4 5 10 9 8 7 6 RW0 SHDN VCC SDI CS
* Pb-free plus anneal product (RoHS compliant)
Ordering Information
PART NUMBER ISL22429UFU10Z (Notes 1, 2) ISL22429WFU10Z (Notes 1, 2) NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add "-TK" suffix for 1,000 Tape and Reel option PART MARKING 429UZ 429WZ RESISTANCE OPTION (k) 50 10 TEMP. RANGE (C) -40 to +125 -40 to +125 PACKAGE 10 Ld MSOP (Pb-free) 10 Ld MSOP (Pb-free) PKG. DWG. # M10.118 M10.118
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL22429 Block Diagram
VCC
SCK SDI SDO CS SPI INTERFACE POWER-UP INTERFACE, CONTROL AND STATUS LOGIC
VCC
WR1
RW1
VCC
SHDN
NONVOLATILE REGISTERS
WR0
RW0
GND
Pin Descriptions
MSOP PIN 1 2 3 4 5 6 7 8 9 10 SYMBOL NC SCK SDO GND RW1 CS SDI VCC SHDN RW0 SPI interface clock input Open drain SPI interface data output Device ground pin "Wiper" terminal of DCP1 Chip Select active low input SPI interface data input Power supply pin Shutdown active low input "Wiper" terminal of DCP0 DESCRIPTION
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FN6332.1 September 26, 2006
ISL22429
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP pin with Respect to GND . . . . . . . -0.3V to VCC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125C ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV
Thermal Information
Thermal Resistance (Typical, Note 3)
JA (C/W)
10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature (Plastic Package). . . . . . . . +150C
Recommended Operating Conditions
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +125C VCC Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -0.8V for all pins.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W option U option MIN TYP (NOTE 5) 10 50 -20 50 80 70 25 +20 MAX UNIT k k % ppm/C (Note 15) ppm/C (Note 15) pF
PARAMETER End-to-End Resistance
End-to-End Resistance Tolerance End-to-End Temperature Coefficient
W and U option W option U option
RW (Note 15) CW (Note 15)
Wiper Resistance Wiper Capacitance
VCC = 3.3V @ +25C, wiper current = VCC/RTOTAL
VOLTAGE DIVIDER MODE (measured at RWi, unloaded; i = 0 or 1) INL (Note 10) DNL (Note 9) ZSerror (Note 7) FSerror (Note 8) VMATCH (Note 11) TCV (Note 12) Integral Non-linearity Differential Non-linearity Zero-scale Error Monotonic over all tap positions Monotonic over all tap positions W option U option Full-scale Error W option U option DCP to DCP Matching Ratiometric Temperature Coefficient Any two DCPs at the same tap position DCP register set to 40 hex -1 -0.5 0 0 -5 -2 -2 4 1 0.5 -1 -1 1 0.5 5 2 0 0 2 LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6) ppm/C
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FN6332.1 September 26, 2006
ISL22429
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 PARAMETER VCC Supply Current (volatile write/read) VCC Supply Current (volatile write/read) ICC2 VCC Supply Current (non-volatile write/read) VCC Supply Current (non-volatile write/read) ISB VCC Current (standby) TEST CONDITIONS 10k DCP, fSPI = 5MHz; (for SPI active, read and write states) 50k DCP, fSPI = 5MHz; (for SPI active, read and write states) 10k DCP, fSPI = 5MHz; (for SPI active, read and write states) 50k DCP, fSPI = 5MHz; (for SPI active, read and write states) VCC = +5.5V, 10k DCP, SPI interface in standby state VCC = +5.5V, 50k DCP, SPI interface in standby state VCC = +3.6V, 10k DCP, SPI interface in standby state VCC = +3.6V, 50k DCP, SPI interface in standby state ISD VCC Current (shutdown) VCC = +5.5V @ +85C, SPI interface in standby state VCC = +5.5V@ +125C, SPI interface in standby state VCC = +3.6V @ +85C, SPI interface in standby state VCC = +3.6V @ +125C, SPI interface in standby state ILkgDig tWRT (Note 15) tShdnRec (Note 15) Leakage Current, at Pins SHDN, SCK, Voltage at pin from GND to VCC SDI, SDO and CS Wiper Response Time after SPI Write to WR Register DCP Recall Time from Shutdown Mode From rising edge of SHDN signal to wiper stored position and RH connection SCK rising edge of last bit of ACR data byte to wiper stored position and RH connection Vpor VccRamp tD Power-on Recall Voltage VCC Ramp Rate Power-up delay VCC above Vpor, to DCP Initial Value Register recall completed, and SPI Interface in standby state Minimum VCC at which memory recall occurs 2.0 0.2 3 -1 1.5 1.5 1.5 2.6 MIN TYP (NOTE 5) MAX 1.4 450 3.5 2.0 1.22 320 800 250 3 5 2 4 1 UNIT mA A mA mA mA A A A A A A A A s s s V V/ms ms
EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 13) Non-volatile Write Cycle Time Temperature T < +55C 1,000,000 50 12 20 Cycles Years ms
SERIAL INTERFACE SPECIFICATIONS VIL VIH SHDN, SCK, SDI, and CS Input Buffer LOW Voltage SHDN, SCK, SDI, and CS Input Buffer HIGH Voltage -0.3 0.7*VCC 0.3*VCC VCC+0.3 V V
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FN6332.1 September 26, 2006
ISL22429
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL Hysteresis VOL Rpu (Note 14) Cpin (Note 15) fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tCS NOTES: 5. Typical values are for TA = +25C and 3.3V supply voltage. 6. LSB: [V(RW)127 - V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)127 - VCC]/LSB. 9. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 10. INL = [V(RW)i - i * LSB - V(RW)]/LSB for i = 1 to 127 11. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 12. TC = --------------------------------------------------------------------------------------------- x ---------------- for i = 16 to 112 decimal, T = -40C to +125C. Max( ) is the maximum value of the wiper V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 165C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 13. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle. 14. Rpu is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates. 15. This parameter is not 100% tested. PARAMETER SHDN, SCK, SDI, and CS Input Buffer Hysteresis SDO Output Buffer LOW Voltage SDO Pull-up Resistor Off-chip IOL = 4mA Maximum is determined by tRO and tFO with maximum bus load Cbus = 30pF, fSCK = 5MHz 10 5 200 100 100 250 250 50 50 10 10 0 20 100 350 0 Rpu = 2k, Cbus = 30pF Rpu = 2k, Cbus = 30pF 2 60 60 TEST CONDITIONS MIN 0.05* VCC 0 0.4 2 TYP (NOTE 5) MAX UNIT V V k
SHDN, SCK, SDI, SDO and CS Pin Capacitance SPI Frequency SPI Clock Cycle Time SPI Clock High Time SPI Clock Low Time Lead Time Lag Time SDI, SCK and CS Input Setup Time SDI, SCK and CS Input Hold Time SDI, SCK and CS Input Rise Time SDI, SCK and CS Input Fall Time SDO Output Disable Time SDO Output Valid Time SDO Output Hold Time SDO Output Rise Time SDO Output Fall Time CS Deselect Time
pF MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
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FN6332.1 September 26, 2006
ISL22429 Timing Diagrams
Input Timing
tCS CS tLEAD SCK tSU SDI MSB tH tWL tCYC tLAG
...
tWH
tFI LSB
tRI
...
SDO
HIGH IMPEDANCE
Output Timing
CS
SCK tV SDO MSB tHO
...
tDIS
...
LSB
SDI
ADDR
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRT MSB
SDI
...
LSB
VW
SDO
HIGH IMPEDANCE
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FN6332.1 September 26, 2006
ISL22429 Typical Performance Curves
VCC
100 90
WIPER RESISITANCE ()
Vcc = 3.3V, T = 125C
1.4
80 70 60 50 40 30 20 10 0 0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
1.2 T =125 C 1
VCC
Isb (A)
0.8
0.6
Vcc = 3.3V, T = 20C
Vcc = 3.3V, T = -40C
0.4 T =25 C 0.2
0 2.7 3.2 3.7 4.2 4.7 5.2
Vcc, V
FIGURE 2. STANDBY ICC vs VCC
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10k (W)
0.2 Vcc = 2.7V 0.1
DNL (LSB) INL (LSB)
0.2
T = 25C
T = 25C 0.1 Vcc = 2.7V
0
0
-0.1 Vcc = 5.5V -0.2 0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
-0.1 Vcc = 5.5V -0.2 0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
1.30 1.10 0.90
ZSerror (LSB)
0.00
10k
-0.30 Vcc = 2.7V
FSerror (LSB)
50k
Vcc = 5.5V
0.70 0.50 0.30 0.10 -0.10 -0.30 -40 -20 0 50k Vcc = 5.5V Vcc = 2.7V
-0.60 -0.90 10k -1.20 -1.50 -40
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. ZSerror vs TEMPERATURE
FIGURE 6. FSerror vs TEMPERATURE
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FN6332.1 September 26, 2006
ISL22429 Typical Performance Curves
END TO END RTOTAL CHANGE (%)
(Continued)
105
1.00 Vcc = 2.7V 0.50
TCv (ppm/C)
50k
90 75 60 45 30 15 0
10k
0.00
-0.50 Vcc = 5.5V -1.00 -40 10k
50k
-20
0
20
40
60
80
100
120
16
36
56
76
96
TEMPERATURE (C)
TAP POSITION (DECIM AL)
FIGURE 7. END TO END RTOTAL % CHANGE vs TEMPERATURE
FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm
FIGURE 9. MIDSCALE GLITCH, CODE 80h TO 7Fh
FIGURE 10. LARGE SIGNAL SETTLING TIME
Pin Description
Potentiometer Pins
RWi (i = 0, 1) RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. SHDN The SHDN pin forces the resistors to end-to-end open circuit condition and shorts RWi to GND. When SHDN is returned to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically OR'd with SHDN bit in ACR register. SPI interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation.
FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE
RW
Bus Interface Pins
Serial Clock (SCK) This is the serial clock input of the SPI serial interface. Serial Data Output (SDO) The SDO is an open drain serial data output pin. During a read cycle, the data bits are shifted out at the falling edge of the serial clock SCK, while the CS input is low.
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ISL22429
SDO requires an external pull-up resistor for proper operation. Serial Data Input (SDI) The SDI is the serial data input pin for the SPI interface. It receives device address, operation code, wiper address and data from the SPI external host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. Chip Select (CS) CS LOW enables the ISL22429, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power up. When CS is HIGH, the ISL22429 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. memory reading, all WRs will be reload with the value stored in corresponding non-volatile Initial Value Registers (IVRs). The SPI interface register address bits have to be set to 0000b or 0001b to access the WR of DCP0 or DCP1 respectively. The WRi and IVRi can be read or written to directly using the SPI serial interface as described in the following sections.
Memory Description
The ISL22429 contains seven non-volatile and three volatile 8-bit registers. The memory map of ISL22429 is on Table 1. The two non-volatile registers (IVRi) at address 0 and 1, contain initial wiper value and volatile registers (WRi) contain current wiper position. In addition, five non-volatile General Purpose registers from address 2 to address 6 are available.
TABLE 1. MEMORY MAP ADDRESS 8 7 6 5 4 3 2 1 0 General Purpose General Purpose General Purpose General Purpose General Purpose IVR1 IVR0 NON-VOLATILE -- Reserved Not Available Not Available Not Available Not Available Not Available WR1 WR0 VOLATILE ACR
Principles of Operation
The ISL22429 is an integrated circuit incorporating two DCPs with its associated registers, non-volatile memory and the SPI serial interface providing direct communication between host and potentiometers and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi is recalled and loaded into the corresponding WRi to set the wiper to the initial value.
The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described below in Table 2. The VOL bit (ACR[7]) determines whether the access is to wiper registers WRi or initial value registers IVRi.
TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT #
Bit Name
DCP Description
Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer and internally connected to Vcc and GND. The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[6:0] = 00h), its wiper terminal (RW) is closest to GND. When the WR register of a DCP contains all ones (WR[6:0] = 7Fh), its wiper terminal (RW) is closest to VCC. As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to GND to the closest to VCC. While the ISL22429 is being powered up, all two WRs are reset to 40h (64 decimal), which locates RW roughly at the center between GND and Vcc. After the power supply voltage becomes large enough for reliable non-volatile
7
VOL
6
SHDN
5
WIP
4 0
3 0
2 0
1 0
0 0
If VOL bit is 0, the non-volatile IVRi register is accessible. If VOL bit is 1, only the volatile WRi is accessible. Note, value is written to IVRi register also is written to the WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. This bit is logically OR'd with SHDN pin. When this bit is 0, DCPs are in Shutdown mode. The default value of SHDN bit is 1. The WIP bit (ACR[5]) is read only bit. It indicates that non-volatile write operation is in progress. The WIP bit can be read repeatedly after a non-volatile write to determine if the write has been completed. It is impossible to write to the IVRi, WRi or ACR while WIP bit is 1.
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ISL22429
SPI Serial Interface
The ISL22429 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL22429. SCK and CS lines are controlled by the host or master. The ISL22429 operates only as a slave device. All communication over the SPI interface is conducted by sending the MSB of each byte of data first. following by Data Byte is sent to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. For a write to addresses 0000b or 0001b, the MSB at address 8 (ACR[7]) determines if the Data Byte is to be written to volatile or both volatile and non-volatile registers. Refer to "Memory Description" and Figure 12. Device can receive more than one byte of data by auto incrementing the address after each received byte. Note after reaching the address 0110b, the internal pointer "rolls over" to address 0000b. The internal non-volatile write cycle starts after rising edge of CS and takes up to 20ms. Thus, non-volatile registers must be written individually.
Protocol Conventions
The first byte sent to the ISL22429 from the SPI host is the Identification Byte. A valid Identification Byte contains 0101 as the four MSBs, with the following four bits set to 0.
TABLE 3. IDENTIFICATION BYTE FORMAT 0 (MSB) 1 0 1 0 0 0 0 (LSB)
Read Operation
A read operation to the ISL22429 is a three-byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte following by "dummy" Data Byte is sent to SDI pin. The SPI host reads the data from SDO pin on falling edge of SCK. The host terminates the read operation by pulling the CS pin from LOW to HIGH (see Figure 13). The ISL22429 will provide the Data Bytes to the SDO pin as long as SCK is provided by the host from the registers indicated by an internal pointer. This pointer initial value is determined by the register address in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 0110b, the pointer "rolls over" to 0000b, and the device continues to output the data for each received SCK clock. In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again.
The next byte sent to the ISL22429 contains the instruction and register pointer information. The four MSBs are the instruction and four LSBs are register address (see Table 4).
TABLE 4. IDENTIFICATION BYTE FORMAT 7 I3 6 I2 5 I1 4 I0 3 R3 2 R2 1 R1 0 R0
There are only two valid instruction sets: 1011(binary) - is a Read operation 1100(binary) - is a Write operation
Write Operation
A Write operation to the ISL22429 is a three-byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte
CS
SCK
SDI 0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 R3 R2 R1 R0 0 D6 D5 D4 D3 D2 D1 D0
FIGURE 12. THREE BYTE WRITE SEQUENCE
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FN6332.1 September 26, 2006
ISL22429
CS SCK SDI 0 SDO 0 FIGURE 13. THREE BYTE READ SEQUENCE D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 R3 R2 R1 R0
Don't Care
Applications Information
Communicating with ISL22429
Communication with ISL22429 proceeds using SPI interface through the ACR (address 1000b), IVRi (addresses 0000b, 0001b) and WRi (addresses 0000b, 0001b) registers. The wiper of the potentiometer is controlled by the WRi register. Writes and reads can be made directly to these registers to control and monitor the wiper position without
any non-volatile memory changes. This is done by setting MSB bit at address 1000b to 1. The non-volatile IVRi stores the power up value of the wiper. IVRs are accessible when MSB bit at address 1000b is set to 0. Writing a new value to the IVRi register will set a new power up position for the wiper. Also, writing to this register will load the same value into the corresponding WRi as the IVRi. Reading from the IVRi will not change the WRi, if its contents are different.
Examples:
B. Reading from the WR:
This sequence will read the value from the WR1 (volatile): Write to ACR first to access the volatile WRs Send the ID byte, Instruction Byte, then the Data byte 010100001100100
0
1100 (Sent to SDI)
0
0
0
0
Read the data from WR1 (Addr 0001b) Send the ID byte, Instruction Byte, then Read the Data byte 0101000010110001xxxxx (Out on SDO)
x
x
x
A. Writing to the IVR:
This sequence will write a new value (77h) to the IVR0(non-volatile): Set the ACR (Addr 1000b) for NV write (40h) Send the ID byte, Instruction Byte, then the Data byte 010100001100100 Set the IVR0 (Addr 0000b) to 77h Send the ID byte, Instruction Byte, then the Data byte 010100001100000
0
0100 (Sent to SDI)
0
0
0
0
0
0111 (Sent to SDI)
0
1
1
1
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FN6332.1 September 26, 2006
ISL22429 Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 0.187 0.016 10 0.003 0.003 5o 0o 15o 6o MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 0.199 0.028 A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 4.75 0.40 10 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 0 12/02
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -C-
R1 R
b c D E1
A
A2
4X
L L1
e E L L1 N R
0.020 BSC
0.50 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6332.1 September 26, 2006

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